This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2002-012369 filed on Jan. 22, 2002; the entire contents of which are incorporated herein by reference.
The present invention relates to a power control semiconductor device. In particular, the present invention relates to a package structure for a compression bonding semiconductor chip.
In general, power control semiconductor devices include an Insulated Gate Bipolar Transistor (IGBT) and an Injection Enhanced Gate Transistor (IEGT). The IGBT and IEGT have MOS structures. High-power switching control for the IGBT and IEGT can be performed by control terminals (to be referred to as xe2x80x9cgate terminalsxe2x80x9d hereinafter).
These power semiconductor devices can block a voltage higher than that of a conventional MOSFET or a bipolar transistor. The maximum operating voltage reaches a level of 6 kV. Like the MOSFET, the power semiconductor device has an advantage of voltage driving by a gate terminal. In addition, the power semiconductor device is characterized by a small conducting loss. According to these characteristics, the power semiconductor devices are popularly used.
A conventional power semiconductor device has an emitter copper post, an emitter buffer plate, power control semiconductor chips (to be referred to as xe2x80x9csemiconductor chipsxe2x80x9d hereinafter) such as an IGBT and an IEGT, a collector buffer plate, and a collector copper post. The emitter buffer plate is arranged on the emitter copper post. The semiconductor chip is arranged on the emitter buffer plate. A collector buffer plate is arranged on the semiconductor chip. The collector copper post is arranged on the collector buffer plate. When a force is applied to the emitter copper post and the collector copper post to compress the emitter copper post and the collector copper post to each other, the emitter copper post, the emitter buffer plate, and the semiconductor chip are compression-bonded to each other. The semiconductor chip, the collector buffer plate, and the collector copper post are also compression bonded to each other. The emitter copper post, the emitter buffer plate, and the semiconductor chip are electrically and thermally connected to each other. The semiconductor chip, the collector buffer plate, and the collector copper post are electrically and thermally connected to each other.
However, an increase in compression bonding force per semiconductor chip may decrease the turn-off current handling capability of the power control semiconductor device. The power control semiconductor device includes semiconductor chips. The semiconductor chips are electrically connected to each other in parallel. Desirably, all the semiconductor chips operate evenly at turn-off. However, there are time delays and instabilities. The semiconductor chips do not necessarily operate evenly. The earlier power control semiconductor device had a turn-off current handling capability that is only half of the product of a number of the semiconductor chips and a turn-off current capability of one of the semiconductor chips.
A semiconductor device according to embodiments of the present invention includes a first conductor having a plane surface, semiconductor chips each having a first surface arranged adjacent the plane surface, and having a first main electrode arranged on the first surface and electrically connected to the first conductor, a second main electrode arranged on a back surface of the first surface, and a control electrode arranged on the back surface of the first surface and configured to switch a current flowing between the first main electrode and the second main electrode, a second conductor electrically connected to the second main electrode and having columns each having an upper surface arranged below each of the semiconductor chips and equal to the number of the semiconductor chips, and a circuit board having openings penetrated by the columns, the number of the openings being equal to the number of the semiconductor chips and having a first insulating film, a first conductive film arranged on a peripheral portion of the first insulating film on a second surface of the first insulating film and electrically connected to one of the control electrode and the second conductor, and a second conductive film arranged on a back surface of the second surface of the first insulating film and the peripheral portion above the first conductive film and electrically connected to the other of the control electrode and the second conductor.
A semiconductor device according to embodiments of the present invention includes a first conductor having a plane surface, a first conductive plate arranged on the plane surface and electrically connected to the first conductor, semiconductor chips each having a first surface arranged on the first conductive plate, and having a first main electrode arranged on the first surface and electrically connected to the first conductor, a second main electrode arranged on a back surface of the first surface, and a control electrode arranged on the back surface of the first surface and configured to switch a current flowing between the first main electrode and the second main electrode, second conductive plates equal to the number of the semiconductor chips arranged on the back surface of the first surface electrically connected to the second main electrode, a pressure applied by a peripheral portion to one of the semiconductor chips configured to be a maximum of twice a mean pressure applied by one of the second conductive plates to the one of the semiconductor chips, and a second conductor electrically connected to the second main electrode and having columns equal to the number of the semiconductor chips and having upper surfaces arranged on the second conductive plate.